This invention relates generally to thin-film transistor (TFT) processes and fabrication, and more particularly, to a TFT polycrystalline film, and method of forming large grain sheets of polycrystalline silicon using transition metals semiconductor compounds, such as nickel silicide, to induce the crystallizing of an amorphous film through lateral growth from selective locations on a silicon wafer.
The demand for smaller electronic consumer products with higher resolution displays, spurs continued research and development in the area of liquid crystal displays (LCDs). The size of LCDs can be decreased by incorporating the large scale integration (LSI) and very large scale integration (VLSI) driver circuits, presently on the periphery of LCDs, into the LCD itself. The elimination of externally located driving circuits and transistors will reduce product size, process complexity, a number of process steps, and ultimately the price of the product in which the LCD is mounted.
The primary component of the LCD, and the component that must be enhanced for further LCD improvements to occur, is the thin-film transistor (TFT). TFTs are typically fabricated on a transparent substrate such as quartz, glass, or even plastic. TFTs are used as switches to allow the various pixels of the LCD to be charged in response to the driver circuits. TFT performance will be improved, and driver circuit functions incorporated into TFTs, by increasing the electron mobility in the TFT devices. Increasing the electron mobility of a transistor results in a transistor having faster switching speeds. Improved TFTs having increased electron mobility yield smaller LCD screens, lower power consumption, and faster transistor response times. Further LCD resolution enhancements will require that the TFTs mounted on the transparent substrates have electron mobility characteristics rivaling IC driver circuits currently mounted along the edges of the screen. That is, display and driver TFT located across the entire display must operate at substantially the same level of performance.
The carrier mobility of typical thin-film transistors, with active areas formed from amorphous film, is poor, on the order of 0.1 to 0.2 cm2/Vs. Carrier mobility is improved by using crystallized silicon. Single crystal silicon transistors, which are usually used in TFT driver circuits, have electron mobilities on the order of 500 to 700 cm2/Vs. Polycrystalline silicon transistor performance is between the two extremes, having mobilities on the order of 10 to 400 cm2/Vs. Thin-film transistors having mobilities greater than 100 cm2/Vs would probably be useful in replacing LCD periphery mounted driver circuitry. However, it has been difficult to produce polycrystalline TFTs with electron mobilities of even 40 to 50 cm2/Vs.
Single crystal silicon films, for use with LCDs, are difficult to fabricate when adhered to relatively fragile transparent substrates. A quartz substrate is able to withstand high process temperatures, but it is expensive. Glass is inexpensive, but is easily deformed when exposed to temperatures above 600xc2x0 C. for substantial lengths of time. Even the fabrication of polycrystalline silicon transistors has been very difficult due to the necessity of using low temperature crystalline processes when glass is involved. Current polycrystallization processes typically require annealing times of approximately 24 hours, at 600xc2x0 C., to produce TFTs having a mobility of approximately 30-50 cm2/Vs. These processes are not especially cost effective due to the long process times, and the TFTs produced are not suitable for LCD driver circuits.
The process of heating amorphous silicon to form crystallized silicon is not entirely understood, and research on the subject continues. Variations in temperature, film thickness, the degree to which the amorphous matter melts, impurities in the film, and a range of other factors influence the annealing of amorphous silicon. Generally, large grains of crystallization, or crystallization able to support high carrier mobilities, occur in a polycrystalline film at a specific temperature near the melting point. Temperatures below this preferred temperature do not melt the amorphous silicon enough to form large grain areas, or to form uniformly crystallized film. Temperatures above the preferred temperature rapidly lead to bulk nucleation. The bulk nucleation of amorphous matter results in the spontaneous crystallization of an amorphous film into relatively small grain sizes so that the electron mobility is relatively poor.
Various annealing methods exist for turning amorphous silicon into polycrystalline silicon. The direct deposition of amorphous silicon film is probably the cheapest method of fabricating TFTs. Typically, the transparent substrate is mounted on a heated susceptor. The transparent substrate is exposed to gases which include elements of silicon and hydrogen. The gases decompose to leave solid phased silicon on the substrate. In a plasma-enhanced chemical vapor deposition (PECVD) system, the decomposition of source gases is assisted with the use of radio frequency (RF) energy. A low-pressure (LPCVD), or ultra-high vacuum (UHV-CVD), system pyrolytically decomposes the source gases at low pressures. In a photo-CVD system the decomposition of source gases is assisted with photon energy. In a high-density plasma CVD system high-density plasma sources, such as inductively coupled plasma and helicon sources, are used. In a hot wire CVD system the production of activated hydrogen atoms leads to the decomposition of the source gases. However, TFTs made from direct deposition have poor performance characteristics, with mobilities on the order of 1 to 10 cm2/Vs.
Solid phase crystallization (SPC) is a popular method of crystallizing silicon. In this process, amorphous silicon is exposed to heat approaching 600xc2x0 C. for a period of at least several hours. Typically, large batches of LCD substrates are processed in a furnace having a resistive heater source. TFTs made from this crystallization process are more expensive than those made from direct deposition, but have mobilities on the order of 50 cm2/Vs. A rapid thermal anneal (RTA) uses a higher temperature, but for very short durations of time. Typically, the substrate is subjected to temperatures approaching 700 or 800xc2x0 C. during the RTA, however, the annealing process occurs relatively quickly, in minutes or seconds. Glass substrates remain unharmed due to the short exposure time. Because the process is so rapid, it is economical to process the substrates serially. Single substrates can also be brought up to annealing temperatures faster than large batches of substrates. A tungsten-halogen, or Xe Arc, heat lamp is often used as the RTA heat source.
An excimer laser crystallization (ELC) process has also been used with some success in annealing amorphous silicon. The laser allows areas of the amorphous film to be exposed to very high temperatures for very short periods of time. Theoretically, this offers the possibility of annealing the amorphous silicon at its optimum temperature without degrading the transparent substrate upon which it is mounted. However, use of this method has been limited by the lack of control over some of the process steps. Typically, the aperture size of the laser is relatively small. The aperture size, power of the laser, and the thickness of the film may require multiple laser passes, or shots, to finally anneal the silicon. Since it is difficult to precisely control the laser, the multiple shots introduce non-uniformity""s into the annealing process. Further, the wafers must be annealed serially, instead of in a furnace in batches. Although mobilities of over 100 cm2/Vs are obtainable, TFTs made by this method are significantly more expensive than those made by direct deposition or SPC.
Also under investigation is the use of metal, such as aluminum, indium tin oxide, and transition metals such as nickel, cobalt, and palladium to encourage the crystallization of silicon. Nickel seems especially promising, as the lattice mismatch between nickel di-silicide and silicon is small, less than 1%. In general, nickel has been used to reduce the annealing temperature typically required in a conventional solid phase crystallization (SPC) from approximately 600xc2x0 C. to a temperature in the range between approximately 500 to 550xc2x0 C., so that the LCD substrates are less susceptible to shrinkage. The use of nickel also significantly shortens the annealing process times. TFTs made through this process are comparable in cost with those made by the SPC method, and the mobilities of metal-induced TFTs can approach 100 cm2/Vs.
However, metal-induced crystallization requires the deposition of a transition metal on an amorphous silicon film, and annealment of the transition metal with the amorphous silicon. The result of annealing is dependent on how far the transition metal compounds have spread into the amorphous film. The possible results of annealment are unreacted amorphous silicon (or bulk nucleated silicon), unreacted transition metal, mono-silicide, and di-silicide. All of these compounds can induce high leakage currents in a transistor.
Liu et al., U.S. Pat. No. 5,147,826, disclose the deposition of a non-continuous metal film on amorphous silicon so that the annealing temperature can be reduced to approximately 550 to 650xc2x0 C. Fornash et al., U.S. Pat. No. 5,275,851 disclose a method of depositing extensive areas of metal film to silicon, and low annealing temperatures to crystallize silicon. However, neither method fosters the silicide-enhanced lateral crystal growth needed to fabricate polycrystalline silicon TFTs with very high electron mobility. Neither method discloses a method of controlling the lateral growth of silicide to eliminate unreacted metal and silicides in key areas of the transistor.
A method of rapid thermal annealing nickel silicide with amorphous silicon is presented in co-pending U.S. patent Ser. No. 08/879,386, filed Jun. 20, 1997, entitled xe2x80x9cThin-Film Transistor Polycrystalline Film Through Nickel Induced, Rapid Thermal Annealing and Method for Samexe2x80x9d, invented by Masashi Maekawa, which is assigned to the same assignees as the instant application. This patent application discloses the use of an RTA process to increase the quality of the polycrystalline, and to reduce annealing times. However, the invention does not disclose a method of preventing the incursion of nickel into sensitive areas of a transistor.
A method of selectively depositing nickel silicide to crystallize transistor source/drain regions in a two-step annealing process is presented in co-pending U.S. patent Ser. No. 08/893,285, filed Jul. 15, 1997, entitled xe2x80x9cSelective Silicide Thin-Film Transistor and Method for Samexe2x80x9d, invented by Masashi Maekawa, which is assigned to the same assignees as the instant application. However, metal-induced annealment processes, in the later stages of transistor fabrication, can be cumbersome in some applications.
A method of selectively locating nickel nucleation sites to form large crystal grains is presented in co-pending U.S. patent Ser. No. 09/092,831, filed Jun. 5, 1998, entitled xe2x80x9cSelected Site, Metal-Induced, Continuous Crystallization and Method for Samexe2x80x9d, invented by Maekawa et al., which is assigned to the same assignees as the instant application. However, the above-mention invention cannot insure that the crystal grains formed will be large enough to form a transistor.
It would be advantageous if metal-induced annealment processes could be used to fabricate broad areas of high quality polycrystalline films in critical areas of the transistor.
It would be advantageous if transistor active areas could be formed with a transition metal at an early stage of transistor fabrication.
It would be advantageous if the unreacted transition metals and silicide products could be easily removed after annealment.
It would be advantageous if a TFT transistor could be formed from a single crystal grain to enhance performance.
Accordingly, a method for crystallizing an amorphous film into large grains comprising the steps of:
a) depositing a layer of the amorphous film;
b) implanting or depositing (alternatively referred to as doping) a first concentration of transition metal on the amorphous film, to form a first density of transition metal nucleus sites, with the nucleation sites being separated by a first distance, whereby a low density of nucleation sites is formed; and
c) annealing to form large areas of single grain crystallized film, whereby a crystallized film is prepared for the fabrication of a high electron mobility transistors.
An ion implantation method implants transition metal within a rectangular window having a width in the range from 20 to 50 microns and a length of at least 50 microns. The exact length is dependent on the number of crystallization sites to be formed. In this manner, a concentration of transition metal no more than 2xc3x971019 atoms per cubed centimeter, and a density of transition metal nucleus sites no more than 1xc3x97107 square centimeters is maintained. The distance between transition metal nucleus sites is no less than 2 microns.
A diffusion layer is used in a continual transition metal delivery system aspect of the invention. Then, Step b) is performed, at least partially, simultaneously with the performance of Step c). In this manner, transition metal is continually introduced during the annealing process to support the lateral growth of crystallization, without increasing the metal concentration above the defined minimum. An insulator film having a first thickness is deposited over the amorphous film. The transition metal is deposited over the insulator film and selectively etched to form a predetermined window size. Alternately, the insulator film is selectively thinned to define a window with a first thickness before the deposition of metal. Either way, Step c) includes the diffusion of transition metal through the first thickness of insulator film into the amorphous film, whereby the density of transition metal nucleuses is controlled.
When a single crystallized site is to be formed, the ratio of the transition metal window to the first area of crystallized film is in the range from 1:1 to 1:3. When multiple single crystal sites are to be formed, the ratio is greater than 1:1. Step c) includes the first area of crystallized film being in the range from 20 to 8,000 square microns (xcexc2), which is the area of a circle with a diameter in the range between 5 and 100 microns.
A further steps, precedes Step c), of:
b1) ramping the temperature up to the annealing temperature of Step c) at a rate greater than 5 degrees C. per second, whereby the amorphous film is annealed at the intended temperature of Step c) for a larger crystal grain.
Step c) includes using a Rapid Thermal Annealing (RTA) process at a temperature of approximately 720 degrees C. and a time duration of approximately 2 minutes.
A thin-film transistor (TFT) comprising source/drain and channel regions of a single grain of crystallized film material is also provided. The amorphous film is doped with a transition metal at a first concentration, first density of nucleation sites, and a first distance between nucleation sites on an amorphous film. The amorphous film is annealed to form a first area of crystallized film, which is a single grain of crystal. A pattern is etched in the first area of crystallized film to form the source/drain regions, whereby a transistor is formed having high electron mobility and low leakage current in the transistor active areas.